Electronic systems, which are found in computers and other electronic devices, utilize a variety of conductive structures to electrically couple components to one another. One such electronic system is a memory device typically provided as a semiconductor integrated circuit. There are many different types of memory devices including random-access memory (RAM), read-only memory (ROM), synchronous dynamic random-access memory (SDRAM), dynamic random-access memory (DRAM), and non-volatile memory. In non-volatile memory (e.g., NAND flash memory), one way to increase memory density is by using a vertical memory array, which is also referred to as a three-dimensional (3-D) array.
Some vertical memory arrays include layers of conductive material (separated by layers of insulative material) that are used to provide electrical connections (e.g., word lines) so that memory cells in the array may be selected for writing or reading functions. These conductive layers extend into periphery regions about the memory array and overlie interconnects that are in electrical communication with semiconductor devices (e.g., a memory cell, a CMOS device, etc.) in the memory array. Typically, in order to form electrical connections with the interconnects, relatively large portions of the conductive and insulative layers in the periphery are removed in bulk and the voids are filled with insulative material, which is then planarized. Discrete openings are formed in the insulative material to expose the interconnects, which are then filled with conductive material to form the electrical connections with the interconnects.
Reference will now be made to the exemplary embodiments illustrated, and specific language will be used herein to describe the same. It will nevertheless be understood that no limitation of the scope or to specific invention embodiments is thereby intended.